A Wide Band PLL with A High Linearity VCO in Full Range
碩士 === 國立中央大學 === 電機工程學系在職專班 === 103 === In recent years the performance and speed of VLSI circuits grew up with scale-down process, and now the chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The dif...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93436069291416093821 |