Post-Bond Test and Yield-Enhancement Techniques for Logic-DRAM Stacked ICs
碩士 === 國立中央大學 === 電機工程學系 === 103 === Three-dimensional (3D) integration technology using through-silicon via (TSV) has been acknowledged as one integrated circuit (IC) design technology. Logic and dynamic random access memory(DRAM) stacked 3D IC is considered as one effective approach for overcoming...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/368xxs |