All-Digital Clock De-Skew Circuit with Adaptive Loading Using Reused Delay Measurement Technique
碩士 === 國立中央大學 === 電機工程學系 === 103 === In this thesis, a modern all-digital clock de-skew circuit is proposed. It not only can be calibrated by itself according to the variation of output loading, but also be reduced the area by the reused delay measurement technique. The application of the convention...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/u8zef3 |