Optimization of silicon and oxygen flux and oxidation temperature on Ge-nanoball/SiO2/SiGe gate-stacking heterostructure

• Main Authors: Shih-cing Luo, 羅時慶
• Other Authors: Pei-Wen Li
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/75218553670310600596

碩士 === 國立中央大學 === 電機工程學系 === 103 === We demonstrated a unique approach to generate self-organized, self-alignment, and low-cost Ge-nanoball/SiO2/SiGe-shell gate-stacking heterostructures through the selective oxidation of poly-Si0.83Ge0.17 nano-pillars over the Si3N4 buffer layer on the Si substrate, and then would like to realize SiGe MOSFETs based on this designer heterostructure in the near future. It has been previously demonstrated that the interface trap density (Dit) of SiO2/SiGe heterostructure in the designer heterostructure is about 3.5−5.5 × 1011 cm-2eV-1, which is a promising candidate for high-performance Ge MOSFETs. However, 4nm-thick amorphous interfacial oxide layer was generated during thermal oxidation at 900 °C in H2O ambient, which cannot meet the criteria of prevailing CMOS technology with gate oxide less than 1 nm. In this work, we further reduced the thickness of this SiO2 interfacial layer by tuning the oxidation conditions, such as temperature and oxidation ambient. On the other hand, a SOI substrate was also employed to decrease the SiGe-shell thickness and then increase the Ge content in SiGe shell, forming a high-carrier mobility channel. According to a series of experiments with various oxygen fluxes and temperatures in thermal oxidation process as well as different Si substrate to control Si flux, we found the thickness of interfacial SiO2 layer would be significantly reduced with decreasing thermal oxidation/annealing temperature. Meanwhile, gate-oxide quality was also raised as the oxidation temperature decreased, which was confirmed by extensive current-voltage and capacitance-voltage characterizations in MOSC devices. Both results provide great promises for apply the designer gate-stacking heterostructure in Ge MOS applications.