The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs

• Main Authors: Jyun-Yu Tsai, 蔡君昱
• Other Authors: Ting-Chang Chang
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/31956265666848029321

博士 === 國立中山大學 === 物理學系研究所 === 103 === To achieve high speed, the continuous scaling down of metal oxide semiconductor field electrical field transistors is driving conventional SiO2-based dielectric to be only a few atomic layers thick, leading to excessive gate leakage current and reliability issues. To solve the leakage current problem, it is necessary to increase the physical thickness of the gate dielectric. One of the drawbacks of increasing the physical thickness, however, is that drive current will be decreased. Therefore, high-k material is highly recommended over a SiO2 gate insulator to reduce both tunneling gate leakage and power consumption in CMOS circuits. However, charge trapping in high-k gate stacks remains a key reliability issue, since it causes threshold voltage (VTH) shift and drive current degradation due to the filling of pre-existing high-k bulk defects. Additionally, the issue of charge trapping effect has been found to have a great impact on hot carrier degradation (HCD), since hot carriers tend to be injected into the high-k layer, especially in short channel devices. In long channel devices, maximum impact ionization (I.I.) condition-induced interface state generation is mainly located at the drain side and dominated the HCD. Consequently, the first part mainly focuses on abnormal sub-threshold swing degradation under dynamic hot carrier stress (HCS) in HfO2/TiN n-channel MOSFETs. Results indicate that there is no change in subthreshold swing (S.S.) after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field, this can be confirmed by ISE-TCAD simulation tool. Moreover, by capacitance measurement with varying frequency after dynamic HCS, we found the impaired stress field causes most of interface states are mainly concentrated in shallow states. This results in ON state current and transconductance decreases but no significant S.S. degradation after dynamic HCS. The second part, we investigate the channel hot carrier stress in HfO2/Ti1-xNx p-MOSFETs. Generally, the S.S. should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage. However, our experimental data indicate that S.S. has no evident change under CHCS, but threshold voltage shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different VTH behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO2/Ti1-xNx p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to high-k bulk passivate the pre-oxide trap during the annealing process, a device with more nitrogen shows insignificant charge trapping-induced DIBL behavior. Owing to voltage scaling with channel shrinking, HC effects continue to decrease. However, low bias HCS still cause severe damage to devices. In third part, we investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-MOSFETs with high-k/metal gate stacks. Many groups have proposed new models (i.e. single-particle, multiple-particle process) to well explain the HCD in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO2 interface. However, for high-k dielectric devices, experiment results show the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks. Finally, we also study zirconium-doped hafnium oxide impact on HCD at high and low temperatures and first time to use ballistic transport to illustrate why HCD always shows less degradation at low temperature. In nanoscale n-MOSFETs, hot carrier degradation can be diminish by using HfxZr1-xO2 high-k material, because it has less oxygen vacancy at the high-k layer to lead CHE trapping. It is worthy to mention, at 100 K, zirconium-doped in HfO2 become invalid to reduced HCD since the channel hot electron trapping in the deep bulk trap, but zirconium-doped in HfO2 only passivate shallow trap. And we observed two things to illustrate why HCD always shows less degradation at low temperature. One is the injection velocity decreases at low temperature because the population of the energetic carriers is decreased. The other is the ballisticity enhanced at low temperature due to decreased scattering probability (ex. EES) in the channel. Both of them would decelerate devices degradation when low temperature HCS.