Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter
碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. The pipelined...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/xar24k |