Enhancement of interconnection reliability of dielectric layer for wafer level chip scale package
碩士 === 國立中山大學 === 機械與機電工程學系研究所 === 103 === Recently, adopting the polymer-metal and metal-metal combination in the application of package shows the incremental importance. Among of the packaging process, the wafer level chip scale packaging (WLCSP) process with high integration of system was taken s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85sxfe |