Dummy Fill Insertion Considering Density Uniformity Constraint
碩士 === 國立清華大學 === 資訊工程學系 === 103 === As the shrinking of device geometries scale, there is an inevitable need for better planarization of the multilevel interconnect structures. To meet today's advanced lithography methods, we need a planar surface. Or may leads to bad lithography results. CHEM...
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50283128130795917427 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 103 === As the shrinking of device geometries scale, there is an inevitable need for better planarization of the multilevel interconnect structures. To meet today's advanced lithography methods, we need a planar surface. Or may leads to bad lithography results. CHEMICAL MECHANICAL POLISHING(CMP) is the planarizing technique of
options to generate a good planarity result. But there is one problem for CMP to work perfectly, it can not have large stretches of metal or non-metal regions. Dummy fill has been demonstrated to be an effective technique to fix the planarity issue and to improve the manufacturability for advanced integrated circuit (IC) designs. We propose an liner programming (LP) formulation with some new considerations involved to determine the density of each region and an efficient fill insertion flow. Comparing with the experimental achievement for ICCAD 2014 contest benchmarks, we have a comparable result.
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