An Efficient Pipelined VLSI Architecture for Inverse Quantization and Discrete Cosine Transform in H.265/HEVC
碩士 === 國立清華大學 === 資訊工程學系 === 103 === We propose a hardware implementation including coefficient scanning, inverse quantization and inverse discrete cosine transform for HEVC main profile in this thesis. The design supports 4x4, 8x8 and 16x16 sized transform blocks. It includes a scanning unit, a two...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73414226367590215778 |