A Hardware-friendly Error- floor Lowering Technique for High-rate QC-LDPC Codes
碩士 === 國立清華大學 === 電機工程學系 === 103 === Low-density parity-check (LDPC) codes have great performance in water-fall region, but the error-floor phenomenon always excludes LDPC codes from many communication and storage systems. The phenomenon is resulted from some structures in LDPC codes' Tanner gr...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/gu7h96 |