The VLSI Architecture of a Low-Latency High-Throughput Sorted QR Processor for MIMO Systems
碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === This thesis presents the VLSI architecture of a low latency, high throughput Sorted-QR (SQR) decomposition processor for MIMO communication systems. The proposed SQR engine is operating directly on the complex-valued channel matrix to avoid the matrix augmentati...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64416776058972259900 |