Low-Jitter Fast-Acquisition Clock-Generator and Deskew-Buffer Designs for the DFS Applications
博士 === 國立臺灣科技大學 === 電機工程系 === 103 === In this dissertation, a fast-acquisition all-digital PLL (ADPLL) and two all-digital deskew buffers for the DFS applications are designed. First, an ADPLL with a new phase-frequency error compensation technique is introduced first. When the ADPLL operates in the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44122910158315428298 |