Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories

• Main Authors: Hao-Wei Lin, 林浩暐
• Other Authors: Shyue-Kung Lu
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/69071005612914664675

碩士 === 國立臺灣科技大學 === 電機工程系 === 103 === In recent years, very-large-scale integration (VLSI) technology continues to progress very fast. The number of transistors and the density of embedded memories are also increasing rapidly. This result threats the yield and the reliability of embedded memories seriously. Therefore, fault scrambling technique is proposed to improve the yield of embedded memories effectively. Fault scrambling technique is considered a promising way to distribute faulty bits into different codewords such that the number of faulty cells in each codeword is below the protection capability of the EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the scrambling control words and the algorithm for generating control word is too complex to implement in hardware. Therefore, we propose a heuristic algorithm suitable for built-in implementation for the evaluation of control words based on the hardware limitation. The corresponding built-in scrambling analysis (BISA) circuit is also proposed. The BISA module can be easily integrated into the conventional built-in self-repair (BISR) module. In addition, we propose a new architecture with BISA to improve yield without BISR and spare elements. It can save the extra hardware overhead of BISR and spare elements and the yield can achieve more than 90%. According to experimental results, the repair rate is close to software-based exhaustive analysis and the hardware overhead of the BISA is only about 2%. The result shows that the proposed BISA can improve the repair rate significantly with negligible hardware overhead.