Chip Design of an Analog Min-sum LDPC Decoder Employing Pre-detection Method
碩士 === 國立臺北科技大學 === 電子工程系研究所 === 103 === This thesis proposes an analog min-sum LDPC decoder employing pre-detection method. It is based on low-density parity-check code and uses the current mode circuit to achieve. In order to reduce hardware complexity, min-sum algorithm is applied to this decode...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/785558 |