The study of pulse swallow divider with low power consumption
碩士 === 大同大學 === 電機工程學系(所) === 103 === In frequency divider circuit, more power consumption will be required due to higher clock frequency from voltage-control-oscillator (VCO). The basic architecture of the conventional programmable divider (PD) is composed of dual-modulus prescaler (DMP) and two co...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37430187722063596250 |