| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 103 === In frequency divider circuit, more power consumption will be required due to higher clock frequency from voltage-control-oscillator (VCO). The basic architecture of the conventional programmable divider (PD) is composed of dual-modulus prescaler (DMP) and two counters. In related articles, in order to reduce chip area and power consumption, some research adopt only one counter in PD, the others modify the architecture of DMP. In this thesis, despite only one counter is adopted in pulse swallow counter, a switchable comparator is proposed for reducing power consumption. The proposed architecture not only modifies the circuit of DMP, but also controls the turn-on or turn-of of the comparator to reduce the power consumption in DMP and comparator. TSMC 0.18 µm process technology is adopted for circuit simulation. Simulation results show that power consumption compared with [5] can be saved approximately 24% and its maximum operating frequency is about 3.5GHz.
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