Thermal- and Performance- Aware Mapping Algorithm and Architecture Design for Multi-Channel Three-Dimensional DRAM System
碩士 === 元智大學 === 電機工程學系 === 103 === In future SoC design, multi-core computing and heterogeneous integration are two trends. Besides, more and more cores are integrated in a chip, and the requirement of the memory bandwidth also increases rapidly. The TSV-based 3D DRAM system can solve the aforementi...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/8694gn |