A Routability-Driven Placement Prototyping Considering Macro Regularity
碩士 === 國立成功大學 === 電機工程學系 === 104 === As advance of process technologies and widely reuse of intellectual property (IP), a system-on-chip (SoC) design usually contains a large amount of standard cells and several hundred of macros. Due to large difference in size between a standard cell and a macro a...
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| Format: | Others |
| Language: | zh-TW |
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2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/762d48 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 104 === As advance of process technologies and widely reuse of intellectual property (IP), a system-on-chip (SoC) design usually contains a large amount of standard cells and several hundred of macros. Due to large difference in size between a standard cell and a macro and various design consideration, mixed-size placement still remains a quite difficult problem. The paper introduces a routability-driven placement prototyping algorithm for hierarchical mixed-size circuits and pays special attention to regular placement of macros. The three-stage approach is the most popular mix-cell placement algorithm and can best fit into existing commercial design flows, where placement prototyping is the most important stage and locations of macros and standard cells are affected by the result. In addition to normal cells and macros, there exist sets of macros which have identical shapes and similar hierarchy in modern designs. Placement of these macros regularity can facilitate powerplanning and induce better routability. Experimental results have demonstrated effectiveness of our approach in industry benchmarks and actual design flow.
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