Congestion-Aware Powerplanning Methodology Considering IR-Drop Constraint Based on the Hybrid GA-SA Algorithm
碩士 === 國立成功大學 === 電機工程學系 === 104 === Powerplanning is a crucial stage in the physical design. Due to advance in manufacture technology, the number of transistors in a chip increases dramatically which leads to higher power consumption and makes routing more difficult. Since a power network will occu...
Main Authors: | Ming-ChungHu, 胡明全 |
---|---|
Other Authors: | Jai-Ming Lin |
Format: | Others |
Language: | zh-TW |
Published: |
2016
|
Online Access: | http://ndltd.ncl.edu.tw/handle/7x2v5j |
Similar Items
-
Routability-driven Powerplanning with Dynamic Voltage Drop Constraint
by: I-RuChen, et al.
Published: (2019) -
Routability-Driven Macro-Aware Powerplanning Methodology Based on Learning Technique
by: Jhih-ShengSyu, et al.
Published: (2018) -
Floorplanning and Powerplanning for a Multi-Core Chip Considering Multiple Supply Voltages
by: Wei-TingChen, et al.
Published: (2012) -
A Routability-Driven Powerplanning Methodology Based in the Dynamic Programming Algorithm
by: Tzu-ChingWeng, et al.
Published: (2015) -
Voltage-Island Driven IR-Drop Aware Floorplanning Methodology for 3D ICs
by: Po-YangChiu, et al.
Published: (2016)