Study of Sigma-Delta Audio Digital-to-Analog Converter
碩士 === 國立暨南國際大學 === 電機工程學系 === 104 === The purpose of this thesis is to research and design the delta-sigma digital-to-analog converter (Sigma-Delta D/A converter) for audio applications. This system supports sampling rate 48 kHz with 24-bit input. The main clock is 3.072 MHz because of the 64-fold...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10803023963608648547 |