Evaluation of Enhancement Mode InAs HEMTs for RF and Low-Power Logic Applications Using Non-alloyed Ohmic &; Sidewall Etch Process

• Main Authors: Yang, Kai-Chun, 楊凱鈞
• Other Authors: Chang, Yi
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/ns7b82

碩士 === 國立交通大學 === 光電系統研究所 === 104 === In order to extend Moore’s law. The key point lies in maximizing the device on-current, while suppressing the leakage currents. In general, III-V compound semiconductors have significantly higher intrinsic mobility than silicon and the substrates are semi-insulating. These material properties combine with band gap engineering, epitaxial layer growth technique and process technologies result in devices with excellent performance. Recently, High indium content InGaAs-based HEMTs are particularly promising for future high-speed and ultra-low power logic application because the excellent electrical properties of InxGa1-xAs material and the superior band-gap design of HEMTs. In this study, the 100 nm InAs HEMTs processed with sidewall etch process, Ti/Pt/Au non-alloyed ohmic process, two-step recess and Pt gate sinking technologies for RF applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 100 nm InAs HEMTs with these advanced processes exhibit better performance than the conventional InAs HEMTs at low applied voltage such as better current saturation, lower output conductance (go), smaller negative threshold-voltage (VT), higher current-gain cut-off frequency (fT) of 489 GHz. The excellent electronic performances indicate the developed 100 nm InAs HEMTs are suitable for high-gain, low noise and low voltage applications. In addition to high frequency RF applications, the evaluations of 100 nm InAs thin channel HEMTs for high-speed logic applications have also been demonstrated in this study. The devices show outstanding logic performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 50 mV/V, subthreshold swing (SS) is 63.3 mV/decade, and intrinsic gate delay (CV/ION) is less than 0.32 psec, and ION/IOFF higher than 1.3 × 104. These results demonstrate that the E-mode InAs HEMTs have great potential for future high-speed and low-power logic application.