The research and process development of III-V on Si high speed electronic devices

• Main Authors: Chen, Cheng-chin, 陳政勤
• Other Authors: Kuo, Hao-chung
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/74925544897278834537

碩士 === 國立交通大學 === 光電工程研究所 === 104 === In this thesis, we report two compound semiconductor devices: GaN-on-Si high electron mobility transistor (HEMT) and In0.53Ga0.47As-on-Si Fin field effect transistor (FinFET). We have demonstrated the high power GaN HEMT with metal-insulator-semiconductor (MIS) structure. We optimized process details, especially the thermal metallization process for low contact resistance of S/D Ohmic contacts. Furthermore, the interdigitated layout of GaN-on-Si HEMT was also introduced, corresponded to atomic layer deposition (ALD) process to obtain low gate leakage. Regarding the process optimization, the experimental results show that the 8 A of operation current for GaN-on-Si MIS-HEMT was successfully fabricated with 1000 V breakdown voltage and low gate leakage. We also developed the fabrication process of In0.53Ga0.47As FinFET on InP substrate. The top-down etching process was employed to fabricate InGaAs Fin structure. In addition, we optimized the metal gate etching process by modification of gas flow, ICP bias, and gas source. The final result shows that the additional nitrogen gas was required to obtain the vertical sidewall of TiN metal gate. The first demonstration of InGaAs FinFET was also fabricated, shows ~800 mA/mm of IDS at VGS = 2V. The subthreshold swing was calculated about 387 mV/dec, and the device leakage is essential to improve in the future. In summary, we built two basic process flows of III/V-on-Si devices. The III/V-on-Si device will be the candidate of the next generation electric transistors, leading to high power, high speed and low power consumption of high efficiency electronics.