Improving DRAM Cache Hit Rate and Performance via Adaptive Granularity Block Size Management
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 104 === Hit rate and access latency are the two most crucial factors that determine the performance of on-chip stacked DRAM. Various fixed granularity DRAM cache tag design management has been proposed to improve the overall stacked DRAM performance. However, the sma...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5y6v3u |