The Design and Optimization of a Low Power Bi-layer Resistance RAM
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Charge-trapping memory devices (e.g., FLASH, SONOS etc.) have several inherent disadvantages that are difficult to overcome, such as higher operating voltage, charge loss, and mismatch between program and erase. The thickness of tunnel oxide also limits the...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64027912143962399826 |