Traps Induced Reliability Issues in Resistive Random Access Memory and SONOS Flash Memory

• Main Authors: Chung, Yueh-Ting, 鍾岳庭
• Other Authors: Wang, Tahui
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/00401619937660067709

博士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === This dissertation will focus on major reliability issues in random access memory (RRAM) and SONOS flash memory induced by traps in a dielectric. Statistical characterization of SET-disturb failure time in an RRAM crossbar array, random telegraph noise (RTN) and single program charge induced Vt retention loss in SONOS are performed. Monte-Carlo simulation model and numerical simulation model are also developed to corroborate our characterization results. In Chapter 1, first, the evolution of the nonvolatile memory technology in recent years and the major reliability concerns are addressed. Second, the applications and the reliability issues of an RRAM crossbar array will be demonstrated. Also, the impact of single charge phenomenon in SONOS flash memory will be pointed out. The organization of this dissertation will be given in this chapter. In Chapter 2, a new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. To investigate this new degradation mode, we perform constant voltage stress in HRS to characterize trap generation in a switching dielectric by measuring a stress-induced leakage current and low-frequency noise. The constant voltage stress is to emulate high-field stress and thus trap creation in SET/RESET cycling. We find that a low-field current in HRS via trap-assisted tunneling in a rupture region increases gradually in both constant voltage stress and SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A three dimensional Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both stress-generated traps and SET-disturb induced oxygen vacancies. The model can well explain observed abrupt and drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps. In Chapter 3, two more factors affecting SET-disturb failure time (f) including resistance window in operation and SET-disturb voltage are investigated. The dependence of f on resistance window in operation is characterized. We find that f is greatly affected by the current level of LRS. The strong LRS dependence of f is attributed to a small Weibull slope of f. In addition, we perform statistical characterizations of f at different SET-disturb voltages. A relationship between f and a SET-disturb voltage in a stressed cell is given. Statistical characterization of two-level random telegraph noise (RTN) amplitude distribution in a hafnium oxide resistive memory has been performed in Chapter 4. We find that two-level RTN in HRS exhibits a large amplitude distribution tail, as compared to LRS. To investigate an RTN trap position in a hafnium oxide film, we measure the dependence of electron capture and emission times of RTN on applied read voltage. A correlation between an RTN trap position and RTN amplitude is found. Owing to a non-uniform distribution of oxygen vacancy after a RESET process, RTN traps near the cathode are responsible for an RTN large-amplitude tail in HRS mostly. In Chapter 5, a Vt retention distribution tail in a Multi-Time-Program (MTP) SONOS memory is investigated. We characterize a single program charge loss induced Vt in NOR-type multi-level SONOS cells (MLC). Our measurement shows that (i) a single charge loss induced Vt exhibits an exponential distribution in magnitudes, which is attributed to a random program charge induced current path percolation effect and (ii) the standard deviation of the exponential distribution depends on a program charge density and increases with a program Vt level in a MLC SONOS. In addition, we measure a Vt retention distribution in a 512Mb MTP SONOS memory and observe a significant Vt retention tail. A numerical Vt retention distribution model including the percolation effect and a Poisson distribution based multiple charge loss model is developed. Our model agrees with the measured Vt retention distribution in a 512Mb SONOS well. The observed Vt tail is realized mainly due to the percolation effect. Finally, conclusions are made and future work is described in Chapter 6.