Near-Threshold All-Digital Phase-Locked Loop with PVT Compensation Techniques for Low Power Applications
博士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === Due to the demand of fast frequency conversion during the dynamic voltage frequency scaling (DVFS) operation and low power applications, a clock generator with fast lock-in performance and low power consumption is mandatory to provide different frequencies....
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/636wnr |