Investigation of Single Side Heated Chip-to-Wafer Bonding and Low Temperature Asymmetry Hybrid Bonding for 3D Heterogeneous Integration Applications
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 104 === In response to necessity of chip size scaling down, 3D integration applied in advanced packaging procedures becomes more important. The chip level and wafer level bonding are competitive in yield and throughput separately. Because of the usage of known good...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/n9c864 |