Advanced ESD Protection Design for Nanoscale CMOS Processes
博士 === 國立交通大學 === 電機資訊國際學程 === 104 === In order to achieve lower power consumption, higher operating speed, and higher integration capability, the CMOS features were continually scaled down with lower operating voltage, thinner gate oxide thickness, and smaller channel length in CMOS technology. How...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12568380960145843350 |