Real-time and Low-memory Multi-face Detection System Design based on Naive Bayes Classifier using FPGA

• Main Authors: Liu, Chong-Hsien, 劉忠賢
• Other Authors: Chen, Yon-Ping
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/f92z7n

碩士 === 國立交通大學 === 電控工程研究所 === 104 === In recent years, face detection is widely used in various fields, such as face recognition, image focusing, and surveillance systems. This thesis proposes a real-time face detection system based on naive Bayesian classifier using FPGA. The system divided into three main parts, feature extraction, candidates face detection, and false elimination. First downscale the image to the image pyramid and extract local binary image features from each downscaling image; then features go through the naive Bayesian classifier to identify candidate faces. Finally, use skin color filter and face overlapping elimination to remove false positives. Detection results output to the monitor in VGA. In this thesis, face detection system to implement in FPGA. As a result of the FPGA parallel processing, in 640480 resolutions, the face detection of an image executes within 16.7 milliseconds. And the improved local binary features, compared to Haar features, save around 140 times the amount of memory. The experimental results show that the accuracy rate is higher than 95% in face detection, which implies the proposed real-time detection system is indeed effective and efficient.