Parallel Error Correction Logic for BCH Decoder
碩士 === 國立高雄第一科技大學 === 電腦與通訊工程研究所 === 104 === Conventional parallel BCH decoding algorithm is the use of a generator polynomial root into the message of the polynomial to get syndrome,then the syndrome obtained error location polynomial after which an error position Chien search algorithms and error...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20365699876886707595 |