Design Instruction Analyzer in the Hyper-scalar Architecture
碩士 === 國立中山大學 === 電機工程學系研究所 === 104 === When the Hyper-scalar microprocessor system architecture performs the same thread, it cause the delay of data transmit and reduce the performance due to the dependence between instructions which result in a frequently data interact between cores in the Virtual...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/e9bc8r |