Grid Alignment of Gates for Layout Migration to FinFETs
碩士 === 國立清華大學 === 資訊工程學系 === 104 === With the process development, transistors become smaller and more complicated.In 16/14 nm process, FinFETs make a huge progress in electronics industry. Layout migration is an important task in design reuse. In order to migrate the process from 28/20 nm to sub-16...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/11403262429414421419 |