Architectural Evaluations on TSV Redundancy for Reliability Enhancement

• Main Authors: Chiu, Chien Pang, 邱建邦
• Other Authors: Hwang, TingTing
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/24666372683301496822

碩士 === 國立清華大學 === 資訊工程學系 === 104 === Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can transmit through dies vertically. TSV may fail when a chip is working. Hence, reliability is an important issue in design time. TSV redundancy is one of effective methods to enhance reliability. In this paper, we will study the tradeoff of various TSV redundancy architectures in terms of effectiveness and cost. To allow the measurement of reliability more realistic, we propose a new standard, repair rate, to appraise the TSV redundancy architectures. Moreover, to design a more flexible and efficient structure, we enhance the ring-based architecture [1] that can adjust grid size and TSV redundancy.