Performance Optimization of Accelerators using C-based High-Level Synthesis Flow
碩士 === 國立清華大學 === 資訊工程學系 === 104 === High-level synthesis (HLS) has made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. Memory partitioning in HLS can efficiently map data elements in the same logical array onto multiple physical banks. But...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10187876507311394693 |