Controller Design for a Low Power, Low Latency DRAM with Built-in Cache
碩士 === 國立清華大學 === 電機工程學系 === 104 === Memory system’s performance is still a significant bottleneck in today’s computer system due to the memory wall issue. In order to reduce the power and latency, DRAM vendors also hope that they can keep the characteristic of low production cost at the same time....
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57838299454308304636 |