An Efficient Layered Decoder Architecture with Error-Floor Lowering Technique for High-Rate QC-LDPC Codes
碩士 === 國立清華大學 === 電機工程學系 === 104 === Extremely low error rate is required for storage systems. Trapping sets are regarded as the major cause of the error floor of low-density parity-check (LDPC) codes. In this work, a practical method is constructed for lowering the error floor of low-density parit...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/3qgs43 |