Test Cost Reduction Methodology for Integrated Fan-Out Wafer Level Chip Scale Package
碩士 === 國立清華大學 === 電機工程學系 === 104 === The integrated fan-out wafer level chip scale packaging (InFO WLCSP) is one of the emerging packaging technologies to achieving small chip form factor with low manufacturing cost. In InFO WLCSP, copper (Cu) pillars are used as the contact interfaces, which can be...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26437843300124712064 |