Efficient Probing Schemes for Fine-Pitch Pads of InFO Wafer-Level Chip-Scale Package
碩士 === 國立清華大學 === 電機工程學系 === 104 === With the increasing demand of super high scale of integration and small form factor in advanced semiconductor products, especially those that integrate DRAM and logic dies, 3D IC and Wafer-Level Chip-Scale Packaging (WLCSP) are considered promising approaches. In...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/64107426437393956996 |