Low-Temperature Formed Dielectrics and Stacked Vertical Gate on Characteristics of Junctionless Charge Trapping Flash Memory Devices
碩士 === 國立清華大學 === 工程與系統科學系 === 104 === The scaling trend of flash device is limited by the dimension of planar device, which makes the process flow more complex. How to improve the operational characteristics and increase the device density at the same time become two of the most important issues....
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| Format: | Others |
| Language: | zh-TW |
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2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2dys74 |