Fabrication Processes of negative capacitance Self-Aligned Fin Channel Tunneling FETs uing I-Line Photolithography
碩士 === 國立臺灣師範大學 === 光電科技研究所 === 104 === This is experimental demonstration integrating Ge FETs with ferroelectric HfZrOx gate stack for subthreshold swing (SS) < 60mV/dec and hysteresis-free by negative capacitance (NC) effect. The capacitance of semiconductor and ferroelectricity is matched t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64099201069102022903 |