Optimized Two-layer Power-ground Mesh Layout for Power Integrity Improvement on Wafer-level Package
碩士 === 國立臺灣大學 === 電信工程學研究所 === 104 === The next generation wafer-level packaging technology suffers from serious signal and power integrity issues due to lower re-distribution layer (RDL). Because of serious parasitic effects caused by the high-density lower RDL traces, the robust power delivery net...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16601295981385016256 |