A 14Bit 100MS/s Current-Steering Digital to Analog Converter for HDTV
碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === In this thesis, a 14-bit 100MHz segment digital-to-analog converter is proposed. It is implemented in UMC standard 0.18μm 1P6M CMOS technology. The segmented architecture current steering DAC are divided into three parts. First part is a 6bit MSB constructed by...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4ywhvz |