Low-Power SAR ADC Design using Capacitor-Swapping Techniques
碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === This thesis presents a 1.2-V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented and 1.2-V 12-bit 100MS/s successive approximation register analog-to-digital converter. By applying a Capacitor-Swapping Techniques...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2016
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/m6k9x5 |