A Study of Test Schedule Optimization for Multicore SoCs
碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === The sound economic solution is necessary for IC product testing with its increased integration and complexity. The cost saving is significant after test time reduction (TTR) whenever it implements on high product volume. The scheduling simulation evaluates test...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47900026812091503128 |