A Study of Test Schedule Optimization for Multicore SoCs

• Main Authors: Gwo-Tzong Leu, 呂國宗
• Other Authors: Wei-Mei Chen
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/47900026812091503128

碩士 === 國立臺灣科技大學 === 電子工程系 === 104 === The sound economic solution is necessary for IC product testing with its increased integration and complexity. The cost saving is significant after test time reduction (TTR) whenever it implements on high product volume. The scheduling simulation evaluates test items and bus resources for preparing before manufacture. The goal of this study is for the test scheduling to minimize the makespan. We used CPLEX, a tool for ILP, to find optimal solutions for the problems. Meanwhile, we proposed a genetic algorithm (GA) to obtain approximate solutions, which is more time-efficient than CPLEX when the big problem sets. Taguchi method design of experiment (DOE) was used to evaluate the performance of parameter combination of GA for scheduling as well.