| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 104 === For sub-10 nanometer technology nodes, multiple patterning technologies are still the major solutions for pushing the limit of lithography due to the delay of next generation lithography technologies. In this thesis, we propose a triple patterning lithography (TPL)-aware router that guarantees the layout decomposability of via layers. In the research, the router does not perform simultaneous routing and coloring to maximize routing flexibility. To guarantee layout decomposability, we show that considering $K4$ forbidance in the conflict graph alone is not sufficient. We therefore adopt the idea of graph isomorphism and construct a 3-uncolorable graph library in our routing flow. To tackle the high complexity of the graph isomorphism algorithm, we use several graph reduction techniques and propose a via plane division method to minimize the runtime overhead. Finally, an optimal integer linear programming (ILP)-based layout decomposition algorithm is used to show that layout decomposability is ensured by our router. Experimental results show the necessity and effectiveness of our router.
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