The study of Enhancement-mode GaN-based HEMTs formed by Selective-area Ion implantation technology

• Main Authors: CHIANG, KAI-JEN, 江鎧任
• Other Authors: LEE, MING-LUN
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/vk3b3t

碩士 === 南臺科技大學 === 光電工程系 === 104 === Since the wide bandgap GaN/AlGaN heterostructures inherently possess spontaneous and strain-induced polarization fields to induce the high electron mobility and high carrier density at the GaN/AlGaN heterointerfaces, GaN/AlGaN-based high electron mobility transistor (HEMT) is one of the most promising power devices due to its excellent thermal stability and high breakdown field. In fact, GaN/AlGaN-based HEMTs have been extensively demonstrated and launched to practical application such as power amplifiers of wireless communication systems and radar systems. In current practical application, most of the GaN/AlGaN-based HEMTs are normally-on devices because the two-dimensional electron gas (2DEG) in energy is lower than the Fermi level. Consequently, an external negative bias must be applied to the gate to making the transistor at the turn-off situation. In other words, the normally–on transistors will continue to dissipate power even without external gate bias. Therefore, the normally-off GaN/AlGaN-based HEMTs are the key devices for the high-efficiency power mplifiers. In this study, selective-area Si implantation are applied onto the GaN/AlGaN heterostructures grown on Si substrate to selectively convert the p-GaN cap layer into n+-GaN regions, and the drain and source area are formed after post-implantation annealing process. In contrast to the conventional normally-off GaN/AlGaN-based HEMTs, which use etching technique to form recess gate associating with a Schottky contact or Fluorine ion implantation at the gate area, in our design, a planar HEMT structure is in-situ formed by selective-area Si implantation onto the p-GaN cap layer where the drain and source area are simultaneously formed thereon. Since the ion implantation induces crystal damage, different implantation and thermal annealing conditions are applied to the device fabrication to investigate the effect of implantation and thermal annealing on device performance. In addition, the effect of different spacing between the drain and source area and SiO2 passivation layer on the device performance is also investigated in this study.