IO/Bump Placement with Physical IO Pad for Flip-chip Design
碩士 === 元智大學 === 資訊工程學系 === 104 === The advancement of technology scaling enables high-level system integration and performance enhancement. With the flip-chip technology, we are able to alleviate the wire-bonding R/L/C impact to an integrated circuit. However, as the increasing of total number of ch...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/752nq9 |