IO/Bump Placement with Physical IO Pad for Flip-chip Design

• Main Authors: Wei-Chun Hsu, 徐瑋均
• Other Authors: Yi-Yu Liu
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/752nq9

碩士 === 元智大學 === 資訊工程學系 === 104 === The advancement of technology scaling enables high-level system integration and performance enhancement. With the flip-chip technology, we are able to alleviate the wire-bonding R/L/C impact to an integrated circuit. However, as the increasing of total number of chip IOs, IC packaging is required to simultaneously take signal integrity, voltage drop, and electrostatic protection into account. Consequently, the design rules for flip-chip IO become more complex. Traditional routability-driven bump placement may not be effective to overcome the aforementioned challenges nowadays. In this thesis, we propose heuristic algorithms for IO/Bump placement, and dynamic programming based IO/Bump placement algorithms for IO pads and bumps co-design problem. With our proposed technique, the total IO width is reduced for RDL routability enhancement and decoupling capacitor insertion to reduce voltage drop. According to the experimental results, our centered-style dynamic programming based IO/Bump placement reduces the extended IO width by 65.51% and the x-direction routing distance is reduced by 59.84%. Finally, if the non-aligned-style (left-edge) IO/bump alignment is allowed, the extended IO width could be further reduced by 57.53%. With the heuristics for IO/Bump placement, the x-direction routing distance is reduced by 51.14%.