Design and Analysis of Digital to Analog Converter
碩士 === 中原大學 === 電子工程研究所 === 105 === In this paper, a 6-bit 1 GS/s folded R-2R ladder-based current-steering Digital-to-Analog Converter is designed. Design platform is TSMC 0.18μm 1P6M CMOS process. At 1.8 power supply, the power consumption simulation results is 1.93mW. The DNL is ±0.08LSB, the INL...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8mez93 |